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pca9553 4-bit i 2 c led driver with programmable blink rates preliminary data 2002 sep 03 integrated circuits
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2 2002 sep 03 features ? 4 led drivers (on, off, flashing at a programmable rate) ? 2 selectable, fully programmable blink rates (frequency and duty cycle) between 0.15625 and 40 hz (6.4 and 0.025 seconds) ? input/outputs not used as led drivers can be used as regular gpios ? internal oscillator requires no external components ? i 2 c interface logic compatible with smbus ? internal power-on reset ? noise filter on scl/sda inputs ? 4 open drain outputs directly drive leds to 25 ma ? controlled edge rates to minimize ground bounce ? no glitch on power-up ? supports hot insertion ? low stand-by current ? operating power supply voltage range of 2.3 v to 5.5 v ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 150 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offer: so8, tssop8 description the pca9553 led blinker blinks leds in i c and smbus applications where it is necessary to limit bus traffic or free up the i 2 c master's (mcu, mpu, dsp, chipset, etc.) timer. the uniqueness of this device is the internal oscillator with two programmable blink rates. to blink leds using normal i/o expanders like the pcf8574 or pca9554, the bus master must send repeated commands to turn the led on and off. this greatly increases the amount of traffic on the i 2 c bus and uses up one of the master's timers. the pca9553 led blinker instead requires only the initial set up command to program blink rate 1 and blink rate 2 (i.e., the frequency and duty cycle). from then on, only one command from the bus master is required to turn each individual open drain output on, off, or to cycle at blink rate 1 or blink rate 2. maximum output sink current is 25 ma per bit and 100 ma per package. any bits not used for controlling the leds can be used for general purpose parallel input/output (gpio) expansion. power on reset (por) initializes the registers to their default state, all zeroes, causing the bits to be set high (led off). due to pin limitations, the pca9553 is not featured with hardware address pins. the pca95531 and the pca95532 have different fixed i 2 c addresses allowing operation of both on the same bus. pin configuration 1 2 3 45 6 7 8 led0 led1 led2 v ss v dd sda scl led3 sw01035 figure 1. pin configuration pin description pin number symbol function 1 led0 led driver 0 2 led1 led driver 1 3 led2 led driver 2 4 v ss supply ground 5 led3 led driver 3 6 scl serial clock line 7 sda serial data line 8 v dd supply voltage
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 3 ordering information packages temperature range order code topside mark drawing number 8-pin plastic so 40 to +85 c pcA9553-1D 9553-1 sot96-1 8-pin plastic so 40 to +85 c pca9553-2d 9553-2 sot96-1 8-pin plastic tssop 40 to +85 c pcA9553-1Dp p53-1 sot505-1 8-pin plastic tssop 40 to +85 c pca9553-2dp p53-2 sot505-1 standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. i 2 c is a trademark of philips semiconductors corporation. block diagram pwm0 register pwm1 register prescaler 0 register prescaler 1 register i 2 c-bus control ledx input filters scl sda oscillator power-on reset v dd v ss sw01036 1 0 blink0 blink1 note: only one i/o shown for clarity led select (lsx) register input register pca9553 figure 2. block diagram
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 4 device addressing following a start condition the bus master must output the address of the slave it is accessing. the address of the pca9553-1 is shown in figure 3 and pca9553-2 in figure 4. 11 0 0010 slave address sw01037 r/w figure 3. slave address e pca9553-1 11 0 0011 slave address sw01038 r/w figure 4. slave address e pca9553-2 the last bit of the address byte defines the operation to be performed. when set to logic 1 a read is selected while a logic 0 selects a write operation. control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9553 which will be stored in the control register. 0 0 ai b2 b1 b0 0 sw01034 0 auto-increment flag register address reset state: 00h figure 5. control register control register definition b2 b1 b0 register name type register function 0 0 0 input read input register 0 0 1 psc0 read/ write frequency prescaler 0 0 1 0 pwm0 read/ write pwm register 0 0 1 1 psc1 read/ write frequency prescaler 1 1 0 0 pwm1 read/ write pwm register 1 1 0 1 ls0 read/ write led selector register description the lowest 3 bits are used as a pointer to determine which register will be accessed. if the auto-increment flag is set, the three low order bits of the control register are automatically incremented after a read or write. this allows the user to program the registers sequentially. the contents of these bits will rollover to `000' after the last register is accessed. when auto-increment flag is set (ai = 1) and a read sequence is initiated, the sequence must start by reading a register different from 0 (b2 b1 b0 0 0 0) only the 3 least significant bits are affected by the ai flag. unused bits must be programmed with zeroes. input e input register bit 7 6 5 4 3 2 1 0 default x x x x x x x x the input register reflects the state of the device pins. writes to this register will be acknowledged but will have no effect. psc0 e frequency prescaler 0 bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 psc0 is used to program the period of the pwm output. the period of blink0 (psc0 1) 38 pwm0 e pwm register 0 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 the pwm0 register determines the duty cycle of blink0. the outputs are low (led off) when the count is less than the value in pwm0 and high when it is greater. if pwm0 is programmed with 00h, then the pwm0 output is always low. the duty cycle of blink0 is: 256 pwm0 256 psc1 e frequency prescaler 1 bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 psc1 is used to program the period of pwm output. the period of blink1 (psc1 1) 38 pwm1 e pwm register 1 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 the pwm1 register determines the duty cycle of blink1. the outputs are low (led off) when the count is less than the value in pwm1 and high when it is greater. if pwm1 is programmed with 00h, then the pwm1 output is always low. the duty cycle of blink1 is: 256 pwm1 256 ls0 e led selector led3 led2 led 1 led 0 bit 7 6 5 4 3 2 1 0 default 0 1 0 1 0 1 0 1 the lsx led select registers determine the source of the led data. 00 = output is set low (led on) 01 = output is set hi-z (led off default) 10 = output blinks at pwm0 rate 11 = output blinks at pwm1 rate
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 5 power-on reset when power is applied to v dd , an internal power on reset holds the pca9553 in a reset state until v dd has reached v por . at this point, the reset condition is released and the pca9553 registers are initialized to their default states, with all outputs in the off state. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 6). sda scl sw00363 data line stable; data valid change of data allowed figure 6. bit transfer start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 7). system configuration a device generating a message is a transmitter: a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 8). sda scl sw00365 s p sda scl start condition stop condition figure 7. definition of start and stop conditions master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl sw00366 i 2 c multiplexer slave figure 8. system configuration
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 6 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. eac h byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master ge nerates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges h as to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge r elated clock pulse, set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. data output by transmitter scl from master sw00368 data output by receiver 12 89 s start condition clock pulse for acknowledgement acknowledge not acknowledge figure 9. acknowledgement on the i 2 c-bus
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 7 bus transactions 10 12 scl write to register data out from port 345678 sda s0a a a 11000 data 1 slave address data to register start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave t pv data 1 valid sw02002 9 b0 0 0 0 ai 0 b2 b1 command byte figure 10. write to register 0 1 0 0 0 1 0 1 1 0 0 0 1 1 s0 a aa acknowledge from slave r/w acknowledge from slave a p na acknowledge from slave acknowledge from master s data data r/w first byte at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter last byte sw02001 no acknowledge from master 1 slave address data from register data from register slave address auto-increment register address if ai = 1 b0 0 0 0 ai 0 b2 b1 figure 11. read from register 110 00 10 read from port data into port sda s1a a data 1 data 4 slave address data from port data from port start condition r/w acknowledge from slave acknowledge from master stop condition t ps data 4 data 2 p data 3 t ph sw01097 no acknowledge from master na data 1 notes: 1. this figure assumes the command byte has previously been programmed with 00h. 2. pca9553-1 shown. figure 12. read input port register
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 8 application data pca9553 v ss sda scl v dd i 2 c/smbus master sw01039 sda scl led0 led1 3.3 v 5 v led2 led3 figure 13. typical application
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 9 programming example the following example will show how to set led0 and led1 off. it will then set led2 to blink at 1 hz, 50% duty cycle. led3 will be set to blink at 4 hz, 25% duty cycle. pca9553-1 is used in this example. table 1. i 2 c-bus start s pca9553 address c4h psc0 subaddress + auto-increment 11h set prescaler psc0 to achieve a period of 1 second: blink period 1 psc0 1 38 psc0 = 37 25h set pwm0 duty cycle to 50%: 256 pwm0 256 0.5 pwm0 = 128 80h set prescaler pwm1 to achieve a period of 0.25 seconds: blink period 0.25 psc1 1 38 psc1 = 9 09h set pwm1 output duty cycle to 25%: 256 pwm1 256 0.25 pwm1 = 192 c0h set led0 on, led1 off, led2 set to blink at psc0, pwm0, led3 set to blink at pcs1, pwm1 e4h stop p
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 10 absolute maximum ratings in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min max unit v dd supply voltage 0.5 6.0 v v i/o dc voltage on an i/o v ss 0.5 5.5 v i i/o dc output current on an i/o e 25 ma i ss supply current e 100 ma p tot total power dissipation e 400 mw t stg storage temperature range 65 +150 c t amb operating ambient temperature 40 +85 c handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirab le to take precautions appropriate to handling mos devices. advice can be found in data handbook ic24 under o handling mos devices o. dc characteristics v dd = 2.3 to 5.5 v; v ss = 0 v; t amb = 40 to +85 c; unless otherwise specified. typ at 3.3 v and 25 c. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 e 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i = v dd or v ss ; f scl = 100 khz e 350 500 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i = v dd or v ss ; f scl = 0 khz e 1.9 3.0 m a v por power-on reset voltage no load; v i = v dd or v ss e 1.7 2.2 v input scl; input/output sda v il low level input voltage 0.5 e 0.3 v dd v v ih high level input voltage 0.7 v dd e 5.5 v i ol low level output current v ol = 0.4v 3 6.5 e ma i l leakage current v i = v dd = v ss 1 e +1 m a c i input capacitance v i = v ss e 3.7 5 pf i/os v il low level input voltage 0.5 e 0.8 v v ih high level input voltage 2.0 e 5.5 v v ol = 0.4 v; v dd = 2.3 v; note 1 6 9 e ma v ol = 0.4 v; v dd = 3.0 v; note 1 8 11 e ma i o low level out p ut current v ol = 0.4 v; v dd = 5.0 v; note 1 10 14 e ma i ol low le v el o u tp u t c u rrent v ol = 0.7 v; v dd = 2.3 v; note 1 11 14 e ma v ol = 0.7 v; v dd = 3.0 v; note 1 14 18 e ma v ol = 0.7 v; v dd = 5.0 v; note 1 17 24 e ma i l input leakage current v dd = 3.6 v; v i = 0 or v dd 1 e 1 m a c io input/output capacitance e 2.1 5 pf notes: 1. the total current sunk for all i/os must be limited to 100 ma and 25 ma per i/o.
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 11 ac specifications symbol parameter standard mode i 2 c bus fast mode i 2 c bus units min max min max f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start conditions 4.7 e 1.3 e m s t hd;sta hold time after (repeated) start condition 4.0 e 0.6 e m s t su;sta repeated start condition setup time 4.7 e 0.6 e m s t su;sto setup time for stop condition 4.0 e 0.6 e m s t hd;dat data in hold time 0 e 0 e ns t vd;ack valid time for ack condition 2 e 600 e 600 ns t vd;dat (l) data out valid time 3 e 600 e 600 ns t vd;dat (h) data out valid time 3 e 1500 e 600 ns t su;dat data setup time 250 e 100 e ns t low clock low period 4.7 e 1.3 e m s t high clock high period 4.0 e 0.6 e m s t f clock/data fall time e 300 20 + 0.1 c b 1 300 ns t r clock/data rise time e 1000 20 + 0.1 c b 1 300 ns t sp pulse width of spikes that must be suppressed by the input filters e 50 e 50 ns port timing t pv output data valid e 200 e 200 ns t ps input data setup time 100 e 100 e ns t ph input data hold time 1 e 1 e m s notes: 1. c b = total capacitance of one bus line in pf. 2. t vd;ack = time for acknowledgement signal from scl low to sda (out) low. 3. t vd;dat = minimum time for sda data out to be valid following scl low.
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 12 +10% 0% 10% 20% 30% 40% percent variation temperature ( c) 40 +20% 0 +25 +70 +85 max avg min sw01085 figure 14. typical frequency variation over process at v dd = 2.3 v to 3.0 v +10% 0% 10% 20% 30% 40% percent variation temperature ( c) 40 +20% 0 +25 +70 +85 max avg min sw01086 figure 15. typical frequency variation over process at v dd = 3.0 v to 5.5 v
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 13 t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl su00645 figure 16. definition of timing
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 14 so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 15 tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1
philips semiconductors preliminary data pca9553 4-bit i 2 c led driver with programmable blink rates 2002 sep 03 16 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 06-02 document order number:

data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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